Conventional floating gate type non-volatile memory can be selectively programmed to store data, code, or files. Floating gate type non-volatile memory can also be erased and reprogrammed, making this type of memory extremely useful in such applications as programmable logic devices, memories, and digital circuits.
In early floating gate type non-volatile memory, each memory cell was usually made up of multiple transistors, including a floating gate type storage transistor for data storage and a select transistor to enable programming and erasure of the storage transistor. However, in conventional floating gate type non-volatile memory, each memory cell is often made up of a single floating gate MOS transistor, typically an enhancement-mode device. The use of a single transistor improves memory density by reducing the size of the silicon chip required for a given memory size. The floating gate MOS transistor in a memory cell, or memory transistor, is programmed by charging its floating gate with electrons. When programmed, the excess electrons create a negative charge on the floating gate of the memory transistor, preventing or at least substantially reducing current flow through the memory transistor when a normal control voltage is applied to its gate terminal. The electrons remain on the floating gate even when power is removed from the circuit, allowing the memory cell to retain the stored data. The memory transistor is "erased" by removing the excess electrons from its floating gate, thereby allowing the memory transistor to conduct a normal current when a normal control voltage is applied to its gate terminal. Alternatively, the MOS transistor can be a depletion-mode device, in which case the memory cell would be programmed by removing electrons from its floating gate.
The memory cells in a floating gate type non-volatile memory array are typically individually programmable to allow the greatest flexibility in data storage. However, if a select transistor is not included in each memory cell, erasing has typically been a bulk process, in which memory cells are erased in blocks. In the present description, floating gate type non-volatile memory which must be erased in blocks will be referred to as flash memory. The number of memory cells in a block defines how efficiently a specified set of data can be erased from the memory array. The smaller the number of memory cells in a block, the more precisely such blocks can be mapped to the set of data to be erased. A large block often requires erasure of a large number of memory cells outside of the desired set of data to be erased. Such unwanted erasures require subsequent reprogramming of the original data, increasing the time required to modify the flash memory. Therefore, to maximize efficiency in the use of a flash memory, it is desirable to minimize block size, thereby providing as fine a resolution in erasing capability as possible.
In the present description, if the erase resolution is so fine that only the desired data is erased (i.e., it is possible to erase a single bit, a single byte or a single word), the memory is referred to as EEPROM (electrically erasable and programmable read only memory).
FIG. 1 shows a conventional flash memory 10, as described in U.S. Pat. No. 4,366,555, issued Dec. 28, 1982 to Hu. Flash memory 10 includes a 5.times.4 array of floating gate type transistors 101. The control gates in each row of transistors are coupled to an associated row voltage supply (100, 102, 104, 106 and 108) by an associated word line (R.sub.1 -R.sub.5). Similarly, the source terminals in each column of transistors are coupled to an associated column voltage supply (90, 92, 94 and 96) by an associated column line (C.sub.1 -C.sub.4). Finally, the drain terminal of each transistor in array 101 is commonly coupled to drain voltage supply 80.
Flash memory 10 is erased as follows. Column voltage supplies 90, 92, 94 and 96 ground all of the source regions, and drain voltage supply 80 grounds all of the drain regions. Selected row voltage supplies 100, 102, 104, 106 and 108 provide a 25 Volt signal to the associated row lines R.sub.1 -R.sub.5. Under these conditions, any electrons stored in the floating gates of the transistors in the selected rows are discharged by tunneling. Flash memory 10 may therefore be capable of erasing on a row-by-row basis. Hu generally states that the drains of the memory devices could be selectively coupled to provide for selective erasure of individual devices. However, Hu provides no further instruction to indicate the specific manner in which the drains should be coupled to achieve such a result.
FIG. 2 shows another conventional flash memory 200, as described in U.S. Pat. No. 5,199,001, issued Mar. 30, 1993 to Tzeng. Flash memory 200 comprises a 2.times.2 array 201 of floating gate MOS transistors 212. The control gates of the transistors in the first and second rows are commonly coupled to word lines WL0 and WL1, respectively. The source terminals of the transistors in the first and second rows are commonly coupled to source lines SL0 and SL1, respectively. Finally, the drain terminals of the transistors in the first and second columns are commonly coupled to bit lines BL0 and BL1, respectively.
A circuit 240 is provided for selecting the individual source lines SL0 and SL1. Since the source lines SL0 and SL1 can be selected individually, a single row of transistors may receive a voltage on an associated source, thereby electrically erasing the data held by those transistors. The transistors of array 201 can therefore be erased on a row-by-row basis. However, as with flash memory 100 (FIG. 1), no means of erasing less than a single row is described.
Thus, the aforementioned flash memories do not provide an acceptable method or apparatus for erasing and reprogramming individual memory cells. Such bit-level erasing capability would provide desirable flexibility and efficiency in the use of floating gate type non-volatile memory. Accordingly, it is desirable to provide a method for erasing individual memory cells in a floating gate type non-volatile memory, wherein each memory cell comprises a single floating gate type transistor.